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    530 project altera de1 Gefundene Jobs, Preise in EUR

    Need a Verilog expert with knowledge of ALtera Quartus and pipeining.

    €18 (Avg Bid)
    €18 Gebot i.D.
    4 Angebote

    1. You have to teach us about RISC-V microcontroller architecture top to bottom and instructions . 2. You have to teach us about VHDL / VERILOG. 3. You can deal it with logisim software. 4. You have to give support and help us to build RISC-V microcontroller in FPGA. 5. You can take class about these minimum 2 days in online. 6. You will get 4 month to complete this. You will get 150$ as p...

    €192 (Avg Bid)
    €192 Gebot i.D.
    6 Angebote

    [Zur Anzeige der URL Anmelden] have to teach us about RISC-V microcontroller architecture top to bottom and instructions . [Zur Anzeige der URL Anmelden] have to teach us about VHDL / VERILOG. [Zur Anzeige der URL Anmelden] can deal it with logisim software. [Zur Anzeige der URL Anmelden] have to give support and help us to build RISC-V microcontroller in FPGA. [Zur Anzeige der URL Anmelden...

    €27 - €221
    €27 - €221
    0 Angebote

    Tasks and scheduling Interruptions Race Direct access to peripherals

    €157 (Avg Bid)
    €157 Gebot i.D.
    4 Angebote

    Gostaria de uma alteração no plugin Amelia. É um plugin de booking de atividades. Eu possuo uma clinica com algumas salas. hoje o plugin ja possui cadastro de localização, funcionários e agendamento de horário para o funcionário_x_local. (via calendário) Eu gostaria de criar um cadastro de SALA, para cadastrar o numero de salas que...

    €389 (Avg Bid)
    €389 Gebot i.D.
    12 Angebote

    The project's goal is to have two I2S codecs, both at the same samplerate, selectable 48/96/192KHz, connected to a CPLD and the CPLD to provide a TDM protocol for connection to a MCU. Codecs will have 48/96/192KHz, stereo, 32bits sample depth and will work at I2S protocol. Codecs will perform both capture and playback concurrently. The TDM protocol should have 4 slots for channels. Some po...

    €203 (Avg Bid)
    €203 Gebot i.D.
    4 Angebote

    Hi, I need FPGA expert for Altera DE1 Board. I will provide library file, I will share more details in chat. please place bid if you can complete this job. thanks

    €81 (Avg Bid)
    €81 Gebot i.D.
    13 Angebote
    €15 Gebot i.D.
    3 Angebote

    I need to get 4 miliseconds data from AD9226 12bit ADC using ALTERA EP4CE6E22C8 + HY57V561620FTP-H 256Mbit SDRAM when I push a button B1. When I push second time the button B1, to get another 4 ms of data. When I push another button B2, the data from SDRAM must be sent to a CP2102 TTL-USB adapter at 115200 baud rate, so I can donwload data to PC. The aquisition speed needs to be 65MHz.

    €230 (Avg Bid)
    €230 Gebot i.D.
    16 Angebote

    I want long term employee. altera quartus II is needed. its simple project

    €11 / hr (Avg Bid)
    €11 / hr Gebot i.D.
    6 Angebote

    This Project is to code exercises on latches, flip-flops and registers along with switches, lights and multiplexers VHDL -- Quartus Prime Lite 18.1 Quartus. Altera De-Soc board hardware implementation

    €43 (Avg Bid)
    €43 Gebot i.D.
    6 Angebote

    Atualmente estou com site de vendas de ingressos gerenciado por fooevents. dentro do wordpress. Esse site ele disponibiliza alguns temas pré prontos e eu quero altera-los. Já tenho o projeto dos emails prontos, só basta passar para codigo fonte. Não precisa "criar codigo" basta apenas pegar do tema atual. tema padrão, [Zur Anzeige der URL Anmelden]

    €130 (Avg Bid)
    €130 Gebot i.D.
    17 Angebote

    Basic device access subsystem I need help . Someone who can explain me and show me step by step how developpe a Control framework for access to LED, switch and 7-segment display devices for DE1-SoC(Microcontroller) , and then do Miscellaneous Device Drivers.

    €12 / hr (Avg Bid)
    €12 / hr Gebot i.D.
    10 Angebote

    It is a serial data splitter from 1 input source to 16 output sink using FPGA with specification as below: * synchronous data transfer * simplex data transfer (from source to sink), using TxD, RxD, TxClock , RxClock * there are 2 modes of clock operation which is selectable using gpio pin : external clock source or internal clock source * data buffer for input and all output channel * preferable t...

    €455 (Avg Bid)
    €455 Gebot i.D.
    11 Angebote

    The project here is to write multiple conditions/actions using VHDL format, that can all be displayed in 1 single program. And tested on an Altera DE2 board Port mapping could be okay but using relatively basic principles is ideal. That is (all are not required): Case statements Else / ElseIf Signals Variables Shift register Flip Flops Multiplexer / De-multiplexer Multibit adder A...

    €97 (Avg Bid)
    €97 Gebot i.D.
    4 Angebote

    I need a design implemented that utilizes the Altera Max 10 FPGA (document with pins attatched) as a decoder to have an Analog Potentiometer (A/P) control RGB LEDs (document attached). Ideally the potentiometer would control the brightness of one of the colors and be able to switch between red, green, or blue. This does not need to actually be programmed onto the board. The schematic, code, and te...

    €18 (Avg Bid)
    €18 Gebot i.D.
    2 Angebote

    I need a design to be theoretically implemented that utilizes the Altera Max 10 FPGA (document with pins attatched) as a decoder to have an Analog Potentiometer control RGB LEDs (document attached). In addition, I need a rough description of what your inputs/outputs on your design are doing and how the decoder works. What you will provide (An example of your results is shown) - TOP Level Schemat...

    €89 (Avg Bid)
    €89 Gebot i.D.
    3 Angebote

    I need help in making a Frogger game in Verilog and need to use 7-sig Altera board

    €172 (Avg Bid)
    €172 Gebot i.D.
    4 Angebote

    I need help in making a Frogger game in Verilog and need to use 7-sig Altera board

    €177 (Avg Bid)
    €177 Gebot i.D.
    1 Angebote

    Design a UART transmitter to serially transmit data from the DE2 board via the serial link to a PC running a terminal program. The PC should then display the ASCII value of the data transmitted.

    €35 (Avg Bid)
    €35 Gebot i.D.
    9 Angebote

    Hi, I need FPGA HCS08 Expert we will be using HCS08 DE1 MicroController. more details i will share in chat box. please if you have experience relegated to this bid. thanks.

    €124 (Avg Bid)
    €124 Gebot i.D.
    5 Angebote

    Altera de1 board code changing in C language i already have the solution need a new code based on this one so simple change it for me

    €108 (Avg Bid)
    €108 Gebot i.D.
    8 Angebote

    Create a project about a 128x3 (128 words, with 3 bits at each word) single-port RAM in Verilog, simulate the design, and load it into the Cyclone IV chip on the DE0-Nano board. The design uses two push-buttons and one DIP switch as inputs. •One side of the DIP switch clears the memory address (not the memory contents). •The depressing of the first push-button indicates a memory write...

    €58 (Avg Bid)
    €58 Gebot i.D.
    9 Angebote

    I need a small CPU project prepared, to teach and demonstrate CPU construction. It should be able to fit on an Intel Altera. It should use RISC. The key components are the ability to explain why cache's were chosen, why addressing was chosen, and what options existed. 8-bits. It should be built using blocks, such that I can remove a block, and code in my own block, and assuming all is good, w...

    €465 (Avg Bid)
    €465 Gebot i.D.
    5 Angebote

    PART A Create a project about a 128x3 (128 words, with 3 bits at each word) single- port RAM in Verilog, simulate the design, and load it into the Cyclone IV chip on the DE0-Nano board. The design uses two push-buttons and one DIP switch as inputs. One side of the DIP switch clears the memory address (not the memory contents). The depressing of the first push-button indicates a memory wr...

    €120 (Avg Bid)
    €120 Gebot i.D.
    3 Angebote

    PART A Create a project about a 128x3 (128 words, with 3 bits at each word) single- port RAM in Verilog, simulate the design, and load it into the Cyclone IV chip on the DE0-Nano board. The design uses two push-buttons and one DIP switch as inputs. One side of the DIP switch clears the memory address (not the memory contents). The depressing of the first push-button indicates a memory wr...

    €44 (Avg Bid)
    €44 Gebot i.D.
    1 Angebote
    I/O VGA and Input Beendet left

    I am building a maze game from the ground up, the assembler, data path etc. I need some help with the VGA controller and input. This will be an on going project but for this part I need to get the input working. I am using Quartas to write it and Im using the DE1-SoC FPGA Im going to use the PS/2 port for the input using the arrow keys to move the character. For now I would just like to get the i...

    €19 / hr (Avg Bid)
    €19 / hr Gebot i.D.
    2 Angebote

    Create a project about a 128x3 (128 words, with 3 bits at each word) single-port RAM in Verilog, simulate the design, and load it into the Cyclone IV chip on the DE0-Nano board. The design uses two push-buttons and one DIP switch as inputs. •One side of the DIP switch clears the memory address (not the memory contents). •The depressing of the first push-button indicates a memory write...

    €48 (Avg Bid)
    €48 Gebot i.D.
    6 Angebote

    Need an extra eyes to review my Altera design. You must has done a design with Altera Cyclone IV E. If you can show me that you have a design with Cyclone IV E, you are in. What I need from you is to review my Cyclone schematic, it should from 1 to 2 hours total. I had problem with configuration chip with my Cyclone IV E FPGA, need your help.

    €51 / hr (Avg Bid)
    €51 / hr Gebot i.D.
    6 Angebote

    There is a device that uses CAN with an 250k. baudrate It is necessary to read data by a specific ID and send to UART. Also receive data from UART and send by specific ID to CAN. The firmware must be added to the finished Cypress project, which also uses UART. UART 1M baudrate.

    €126 (Avg Bid)
    €126 Gebot i.D.
    5 Angebote

    I am using Altera DE2-115 FPGA board to configure it using Quartus software 17 lite edition. We have to use QSYS to assign addresses and link the processor, then assign inputs and outputs in VHDL and pin planner in Quartus, and then use NIOS II processor for Eclipse to write a program in C and run the board. I am seeking some help in building this mini thing. I am attaching a pdf file for the tas...

    €21 / hr (Avg Bid)
    €21 / hr Gebot i.D.
    9 Angebote

    I require a working code in verilog/VHDL/C for an FIR Filter to be implemented on an Altera FPGA

    €101 (Avg Bid)
    €101 Gebot i.D.
    10 Angebote

    I am currently using Altera DE2-115 FPGA board to configure it using Quartus 17 lite edition software and write the code in VHDL. We have to use QSYS, and NIOS II for Eclipse to write a program in C and to run the board. I am seeking some help in building this mini thing.

    €22 (Avg Bid)
    €22 Gebot i.D.
    1 Angebote
    Program a project Beendet left

    I am a worker for a software company. I am currently using Altera DE2-115 FPGA board to configure it using Quartus software. We have to use NIOS II processor, QSYS, and Eclipse to write a program and to run the board. I am seeking some help in building this mini thing.

    €15 / hr (Avg Bid)
    €15 / hr Gebot i.D.
    9 Angebote

    Hi Jin :) I have an assignment which I'm not able to get through..I have a small doubt with the VHDL code I have and I just need to fix it.. It won't take more than 15 mins for you hopefully. The code emulates a vending machine on an ALTERA DE2-115 Board and the push buttons simulate an insertion of a coin..and the incremented value is displayed on the 7 segment display and when the val...

    €27 - €27
    €27 - €27
    0 Angebote

    Hi Nick :) I have an assignment which I'm not able to get through..I have a small doubt with the VHDL code I have and I just need to fix it.. It won't take more than 15 mins for you hopefully. The code emulates a vending machine on an ALTERA DE2-115 Board and the push buttons simulate an insertion of a coin..and the incremented value is displayed on the 7 segment display and when the va...

    €27 - €27
    €27 - €27
    0 Angebote

    Hi Jin :) I have a small doubt with the VHDL code I have and I just need to fix it.. It won't take more than 15 mins for you hopefully. The code emulates a vending machine on an ALTERA DE2-115 Board and the push buttons simulate an insertion of a coin..and the incremented value is displayed on the 7 segment display..however my code is glitchy...if you could help me fix it it'd be a life...

    €27 - €27
    €27 - €27
    0 Angebote

    Eu preciso do HTML e CSS de um site bem simples. Onde os dados do menu carregarão na div da direita. Animações e JS eu posso fazer, eu só preciso de muita ajuda no CSS e que o site seja responsivo. A estrutura está anexada. O único conteúdo que se altera entre as páginas é texto e será carregado por JS na div da direita. I ne...

    €35 (Avg Bid)
    €35 Gebot i.D.
    2 Angebote

    Pipelined dual thread core processor design using system verilog, quartus software and altera development board. Please read pdf for detailed information.

    €145 (Avg Bid)
    €145 Gebot i.D.
    4 Angebote
    FPGA verilog UART Beendet left

    I want the verilog UART code along with pin assignment, synthesis and waveform outputs using Quartus II tool on ALTERA DE2 Board.

    €43 (Avg Bid)
    €43 Gebot i.D.
    3 Angebote

    A project to implement a calculator(ALU) in Verilog code using Quartus program I need a detailed report with state diagram and finite state machine I need one who can access my computer to teach me how to do the settings of the program also the Verilog code will be implemented on ALTERA board(DE2-115) also I need instructions of how I can run on the board (its due Saturday sharp)

    €53 (Avg Bid)
    €53 Gebot i.D.
    6 Angebote

    Project is to create C/C++ software to program Altera FPGA (MAX10) configuration memory from an embedded ARM processor using Altera JAM tools. The target device is MAX10 16M, and embedded CPU is Kinetis. The software must read a JAM file and program the FPGA configuration memory using the JTAG interface, which is bit-banged from the MCU pins. Deliverable is a C/C++ program for the JAM programming...

    €3397 (Avg Bid)
    €3397 Gebot i.D.
    2 Angebote

    I have a project coming up ‪in less than 12 hours‬. I would appreciate if you can help me individually in doing the project in anyway at a deal that shall satisfy your effort. please take a look at the instructions and let me know if you can help: You will use the Altera DE2-115 board (Side note: you only need to design the software and I will install it to the board myself), Quartus II software ...

    €236 (Avg Bid)
    €236 Gebot i.D.
    8 Angebote

    Hi, I need some help on a Altera FPGA testcase. A 16bit bidirectional parallel data interface on FPGA's pins to write/read to/from a 48bit word FIFO. Written in Quartus 18.1 with Verilog/System Verilog. And a testbench for verification. The FPGA pins used are a 16bit bi-directional data bus, a pin for write enable to bus (active low), a pin for read enable from data bus (active low) a chip ...

    €166 (Avg Bid)
    €166 Gebot i.D.
    4 Angebote

    Please find attached file to read more about the project

    €1902 (Avg Bid)
    €1902 Gebot i.D.
    9 Angebote

    To Layout with Altium 8-10 layers board with Altera 484 BGA chip and DDR Memory on it. Will need English speaking guy in order to communicate with Schematic engineer for any pin swapping or other questions during the Layout. Estiamted lead time for the project - 2 weeks (8 hours per day). Attached snapshot on the board with component dumped around it.

    €1087 (Avg Bid)
    €1087 Gebot i.D.
    23 Angebote

    Need to develop a very simple game using VHDL, to be run on an Altera DE1-SoC FPGA board. The game will use as external 4x4 keypad which will be connected to the board via one of the GPIO ports on the board. Also the game will use some 7-segment displays on the board to display some information regarding the game. The game itself is quite simple and straightforward. The rules of the game and other...

    €327 (Avg Bid)
    €327 Gebot i.D.
    4 Angebote

    I have 1.25 Mbps data on an avalon-ST interface to be transferred to the HPS then to the ethernet port on DE1-SOC board. The data are on 24 channels of 24bit samples. I need you to explain the work to me in case I need to modify it or change the platform. My project which collects the data is attached. The top-level file is i2s_dsp

    €39 / hr (Avg Bid)
    €39 / hr Gebot i.D.
    3 Angebote

    I have a de1-soc fpga board ([Zur Anzeige der URL Anmelden]) for the detail. currently i have difficulty id generating code for image processing for my image. I have a completed matlab code that include the image and filtering kernel. I need the code to run into my fpga board.

    €98 (Avg Bid)
    €98 Gebot i.D.
    2 Angebote

    Using Altera DE1-SoC FPGA board, I want you to write a code which can do FFT of the provided signal using Quartus II and Modelsim.

    €338 (Avg Bid)
    €338 Gebot i.D.
    5 Angebote