Filter

Meine letzten Suchanfragen
Filtern nach:
Budget
bis
bis
bis
Typ
Fähigkeiten
Sprachen
    Jobstatus
    325 vlsi project freelancer Gefundene Jobs, Preise in EUR

    Simple CMOS VLSI Design Project (Power, Sequential Timing, Logic Families, Wires & Memory) Look at the problems in: [Zur Anzeige der URL Anmelden] WILL PAY GENEROUSLY. $$$ Project Description is: [Zur Anzeige der URL Anmelden] Reference Literature: CMOS VLSI Design Happy Bidding

    €9 - €177
    €9 - €177
    0 Angebote
    €36 Gebot i.D.
    1 Angebote
    €29 Gebot i.D.
    5 Angebote

    Simple CMOS VLSI Design Project (Power, Sequential Timing, Logic Families, Wires & Memory) MUST BE ACCURATE AND CORRECT. WILL PAY GENEROUSLY. $$$ Project Description is: [Zur Anzeige der URL Anmelden] Reference Literature: CMOS VLSI Design Happy Bidding

    €243 (Avg Bid)
    €243 Gebot i.D.
    2 Angebote

    Simple CMOS VLSI Design Project (Power, Sequential Timing, Logic Families, Wires & Memory) MUST BE ACCURATE AND CORRECT. WILL PAY GENEROUSLY. $$$ Project Description is: [Zur Anzeige der URL Anmelden] Reference Literature: CMOS VLSI Design Happy Bidding

    €137 (Avg Bid)
    €137 Gebot i.D.
    1 Angebote

    I have a Introduction to VLSI Design school course project. I have done most of topics but need to ask a questions and bugs about the project. Need someone to help on this very basic project. Freelancer should known the base sturecture of VLSI lecture. Freelancer either can be student, graduat, postgraduate or more.

    €37 (Avg Bid)
    €37 Gebot i.D.
    8 Angebote

    i have some work related to VLSI and i need someone who can do it in efficient way. Should have good command in designing logic circuit designs. should have good knowledge of CMOS, NMOS transistors etc.

    €24 (Avg Bid)
    €24 Gebot i.D.
    9 Angebote
    abiramiamanm Beendet left

    vlsi coding using QUARTUS II software FPGA

    €17 (Avg Bid)
    €17 Gebot i.D.
    3 Angebote

    I have 1864 technical words. I want to remove the Plagiarism of this work. Current Plagiarism is 82%. I want plagiarism <20%. I have checked plagiarism at turnitin software. I will check final work plagiarism also at turnitin software. Please the bid only those candidates who can work in my given budget. My budget is 200 (INR) for this work. I attached the same file in the attachments.

    €4 / hr (Avg Bid)
    €4 / hr Gebot i.D.
    17 Angebote

    I need someone to create video tutorials for VLSI design from basics to advanced concepts. Advanced Digital Design Concepts CMOS Logic fundamentals RTL Design with Verilog HDL's ASIC Design Systhesis Concepts ASIC Design Stratagies Static Timing Analysis Low power design implementation Design and power Constraints Perl/Shell Scripting EDA tools usage

    €438 (Avg Bid)
    €438 Gebot i.D.
    7 Angebote

    looking for freelancer to develop web content for VLSI training institute. Following tabs required. Home VLSI Courses Offered Custom Layout Design Physical Design Design Verification DFT Placements About us Contact us

    €95 (Avg Bid)
    €95 Gebot i.D.
    12 Angebote

    Hi, I have a Flash 6 bits ADC, would like to attempt to make a 12 bits ADC, can you help me to achieve it ?

    €110 (Avg Bid)
    €110 Gebot i.D.
    16 Angebote

    This is pavan. I am from the VLSI industry. I need a technical writer to explain 3 subjects(digital electronics, Verilog, and VHDL).

    €110 (Avg Bid)
    €110 Gebot i.D.
    17 Angebote

    I need to develop shell script for EDA Tool in VLSI domain

    €74 (Avg Bid)
    €74 Gebot i.D.
    12 Angebote

    Front End VLSI Design engineer Part Time in Bangalore Looking for expert FPGA Design engineer with RTL Design [Verilog] Proven track record of designing, developing, prototyping, and testing high speed FPGA designs Experience in Verilog programming & experience with Xilinx devices and development tools Design Simulation experience [Modelsim] Candidate

    €154 (Avg Bid)
    €154 Gebot i.D.
    12 Angebote

    Front End VLSI Design engineer Part Time in Bangalore Looking for expert FPGA Design engineer with RTL Design [Verilog] Proven track record of designing, developing, prototyping, and testing high speed FPGA designs Experience in Verilog programming & experience with Xilinx devices and development tools Design Simulation experience [Modelsim] Candidate

    €131 (Avg Bid)
    €131 Gebot i.D.
    4 Angebote
    VLSI EDA Cadence Beendet left

    RISC-V CPU chip high performance low power -- run EDA tools to generate GDSII synthesis and place and route

    €33 / hr (Avg Bid)
    €33 / hr Gebot i.D.
    14 Angebote

    Our project relates to vs1005 (All in one audio player on a chip) [Zur Anzeige der URL Anmelden] by [Zur Anzeige der URL Anmelden] in combination with the developer board. Programs are written using VLSI Solution's Integrated Development Environment VSIDE [Zur Anzeige der URL Anmelden] We are coding a VS1005 and want to use a stepper motor

    €115 (Avg Bid)
    €115 Gebot i.D.
    3 Angebote

    An existing algorithm is available, apply it and get the results. Then make minor changes in it for improvement and get the results

    €54 (Avg Bid)
    €54 Gebot i.D.
    5 Angebote
    SD Pro Solutions Beendet left

    ...Engineering and Educational Project provider for Diploma, Engineering (Under Graduate, Post graduates) and Research Scholars. SD Pro was established in the year 2013 for Project Development, Course Designing, Training, and placement guidance, based at South India. SD Pro providers Training and Projects in Embedded systems, VLSI, Matlab, Power systems, Power

    €253 (Avg Bid)
    €253 Gebot i.D.
    4 Angebote

    Please find the document in the attachments. Solve the problems step by step with the given data/parameters and please mention all the steps clearly and specify the units for each and every step correctly and make sure the calculation is perfect. For the first question please draw the circuit diagram on a paper and attach it with the solutions and please make sure all the solutions are in WORD doc...

    €78 (Avg Bid)
    €78 Gebot i.D.
    5 Angebote

    Based on my current design of CDS active pixel, I'd like to have it extended in order to make an implementation of CMOS Image Sensors of array 512x512 at least. You need to make a proof of concept and make simulations of it. We'll use Cadence Virtuoso 6.17

    €195 (Avg Bid)
    €195 Gebot i.D.
    6 Angebote
    Data Collection Beendet left

    ...data. [Zur Anzeige der URL Anmelden] If you want to be sure and on the right page to proceed with this project, you can do a sample of 3 colleges - NIT, IIT and any local college and ping me for a check so we can ensure that you are on the right track. • Go to the website of the mentioned

    €116 (Avg Bid)
    €116 Gebot i.D.
    45 Angebote
    VLSI Trainer Beendet left

    We are looking for an experienced Freelancer trainer who can train on VLSI in Bangalore. The curriculum will be provided by the company for the same.

    €678 (Avg Bid)
    €678 Gebot i.D.
    11 Angebote

    Hello, I have made a SAR 8 bits binairy coded ADC using method of 2 steps Successive Approximation, but it is a bit buggy. I need very experienced engineer in this field, otherwise it would just be loosing time. The simulation must be done in Cadence Virtuoso 6.x Thanks !

    €35 (Avg Bid)
    €35 Gebot i.D.
    2 Angebote

    Design and optimization of low power VLSI circuits for Leakage power reduction using Clock Gating with GSA

    €172 (Avg Bid)
    €172 Gebot i.D.
    4 Angebote

    ...tracking device for a specific application. I am seeking a solution that is an android and IOS application that is designed to track and locate a sensor (IOT, GPS, RF or other VLSI) technology that is embedded within a projectile that is no larger than 1.68-inches (42.7mm) in width, height and length. The IOS and Android applications should be able to

    €281 (Avg Bid)
    NDA
    €281 Gebot i.D.
    20 Angebote

    I want to parse a log file and use regexp to filter some patterns and put them in output log file. I have the script. 1- put the -p and -ig inside text files and feed it to code. like this: [Zur Anzeige der URL Anmelden] -i [Zur Anzeige der URL Anmelden] -o [Zur Anzeige der URL Anmelden] -p [Zur Anzeige der URL Anmelden] -ig [Zur Anzeige der URL Anmelden] [Zur Anzeige der URL Anmelden] is: warnin...

    €95 (Avg Bid)
    €95 Gebot i.D.
    5 Angebote

    Design and optimization of low power VLSI circuits for Leakage power reduction using Clock Gating with GSA

    €163 (Avg Bid)
    €163 Gebot i.D.
    7 Angebote

    Project description is under: [Zur Anzeige der URL Anmelden] Will provide a good reference as well.

    €32 (Avg Bid)
    €32 Gebot i.D.
    5 Angebote

    Sequential Circuit Design Look at the project description, zip files have the actual images. Also attached a reference.

    €30 (Avg Bid)
    €30 Gebot i.D.
    5 Angebote

    Sequential Circuit Design Look at the project description, zip files have the actual images. Also attached a reference.

    €13 - €22 / hr
    €13 - €22 / hr
    0 Angebote

    I need help in VLSI coding language, micro controller , C++ and C

    €374 (Avg Bid)
    €374 Gebot i.D.
    8 Angebote

    Vlsi project on excel

    €20 (Avg Bid)
    €20 Gebot i.D.
    4 Angebote
    magic VLSi Beendet left

    ...schematic of a CMOS 3-input XOR gate. 1- Size the transistors Use the smallest integer widths to achieve ratio of 1(i.e. equal rising and falling resistances) 2- Use Magic VLSI layout tool to Design your layout of the sized design then use irsim to simulate your design (all combinations of input A,B,C). The report should include the following.

    €34 (Avg Bid)
    €34 Gebot i.D.
    5 Angebote
    VLSI homework Beendet left

    everything is clear in the PDF .................................................................................................................................................................................regards

    €44 (Avg Bid)
    €44 Gebot i.D.
    1 Angebote

    i need 3 to 4 papers review for the paper with brief explanation which is related to VLSI electronics

    €143 (Avg Bid)
    €143 Gebot i.D.
    2 Angebote

    Vlsi , clewin program

    €156 (Avg Bid)
    €156 Gebot i.D.
    4 Angebote

    Build a basic building block of the Carry-Skip adder and test it for functionality in LTSpice. Description is in: [Zur Anzeige der URL Anmelden] Reference: [Zur Anzeige der URL Anmelden]

    €25 (Avg Bid)
    €25 Gebot i.D.
    9 Angebote

    Aim is to design a successive approximation register based analog to digital converter using cadence tool (any vlsi back end tool)

    €843 (Avg Bid)
    €843 Gebot i.D.
    8 Angebote
    Logo Design Beendet left

    ...Indian Defence and production agencies. Setup by an experienced team of engineers from the industry to carry-out research, design, development and manufacturing in the field of VLSI and Embedded systems. PCB services from the initial stage of Conception to last stage of Manufacturing and Production are provided with a desire to bring the best within us

    €31 (Avg Bid)
    €31 Gebot i.D.
    20 Angebote

    VLSI developer expertise enhanced in optimization concepts are required

    €452 (Avg Bid)
    €452 Gebot i.D.
    7 Angebote

    ...need a project suggestion for a masters project in VLSI testing and verification using Synopsis EDA tools for sequential circuits, because I have to submit a project proposal. Once a project suggestion seems acceptable, I will need help in finishing the project with desired outputs and compare the same with FPGA implementation. By bid for project...

    €524 (Avg Bid)
    €524 Gebot i.D.
    9 Angebote
    Vlsi project Beendet left

    I need some one has background about VLSI

    €79 (Avg Bid)
    €79 Gebot i.D.
    8 Angebote

    I need help in my company project (more details will be share with shortlisted candidate) You have to be very good in MIPS assembly language RTL, verilog, and basics VLSI technology to be shortlist you have to solve one MIPS Asm. question (attached below) as soon as possible.

    €858 (Avg Bid)
    €858 Gebot i.D.
    5 Angebote

    I am going to do my research so I need useful research ideas in electronics, electrical, IT domains and those who have research ideas in VLSI , Embedded systems, Finfet technology, Drones bid me.

    €57 (Avg Bid)
    €57 Gebot i.D.
    14 Angebote

    Multiplier cell design with the application of 8X8 multiplier, related to VLSI design (very large scale integration). required : some report corrections in chapter 1 and 2 regarding the references and report writing. I have a attached a copy of the report and a paper specifying the corrections.

    €19 (Avg Bid)
    €19 Gebot i.D.
    6 Angebote
    Suggest a topic Beendet left

    Looking for project topics in VLSI testing and verification using Synopsis EDA tools and TETRAMAX for sequential circuits. Once a topic has been selected, I would need help in finishing the project with desired outputs. Finally, I would also need an explanation of the functioning after completing the project.

    €373 (Avg Bid)
    €373 Gebot i.D.
    9 Angebote

    Multiplier cell design with the application of 8X8 multiplier, related to VLSI design (very large scale integration). required : some report corrections in chapter 1 and 2 regarding the references and report writing. I have a attached a copy of the report and a paper specifying the corrections.

    €20 (Avg Bid)
    €20 Gebot i.D.
    4 Angebote

    I need you to develop some software for me. I would like this software to be developed for Windows using Python. floor planning of vlsi module , I have to optimise it using Patrical swarm algorithm , need gui for it It requires 1. formation of model ,i.e placement of [Zur Anzeige der URL Anmelden] with a big block 2. if there are 4 block within a big block then there

    €163 (Avg Bid)
    €163 Gebot i.D.
    4 Angebote