Verilog is a description language used in the field of semiconductor and electronic design. It is also used in analog and mixed-signal circuits. VHDL is a hardware description language used in electronic design automation and integrated circuits. If your business is working with Verilog / VHDL then you can use some freelancer help to ease the workload. Post your Verilog/VHDL job today to connect with such freelancers. Verilog / VHDL Designers anheuern

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    16 Gefundene Jobs, Preise in EUR

    Design a circuit in Logisim for the following simple vending coffee machine: It accepts only coins of the nominal 10 coin and 50 coin . There are two types of coffee, costing: 120 coin and 50 coin. You can order a coffee only when there is enough money (use LED to indicate that you can order one or another type). Once you order, all the money is used without returning any.

    €31 (Avg Bid)
    €31 Gebot i.D.
    5 Angebote

    The parking system has 4 levels, level 1 for admins and disabled, level 2 for staff and disabled, level 3 for visitors and disabled, level 4 for visitors.. we two gates in each level (the gate is a pair of IR sensor) , one gate for entrance and the other for exit.. moreover we have camera and monitor near the entrance gate of level 1 , the camera detects the type of car that entering the parking a...

    €169 (Avg Bid)
    €169 Gebot i.D.
    4 Angebote
    €36 Gebot i.D.
    1 Angebote

    VHDL implemented in altera de2 board

    €440 (Avg Bid)
    €440 Gebot i.D.
    1 Angebote

    Our group wants to implement a game using altera de2 cyclone ii board. Please see the attached file for the details of the game to be implemented.

    €9 (Avg Bid)
    €9 Gebot i.D.
    1 Angebote

    A very simple processor is designed, need to write vhdl codes(few components already written) for it and implement the microprogrammed Control unit.

    €22 (Avg Bid)
    €22 Gebot i.D.
    4 Angebote
    FPGA, VDHL coding 5 Tage left
    VERIFIZIERT

    Please contact me if you expert In FPGA, VDHL coding

    €148 (Avg Bid)
    €148 Gebot i.D.
    9 Angebote

    The project has a few basic functions. 1. maintain a specific temperature 2. fire a signal to a solenoid valve in particular (adjustable) intervals. other basic functions like on off etc

    €164 (Avg Bid)
    €164 Gebot i.D.
    38 Angebote

    Verilog simulation of two action-reaction processes

    €26 (Avg Bid)
    €26 Gebot i.D.
    4 Angebote

    The parking system has 4 levels, level 1 for admins and disabled, level 2 for staff and disabled, level 3 for visitors and disabled, level 4 for visitors.. we two gates in each level (the gate is a pair of IR sensor) , one gate for entrance and the other for exit.. moreover we have camera and monitor near the entrance gate of level 1 , the camera detects the type of car that entering the parking a...

    €128 (Avg Bid)
    €128 Gebot i.D.
    7 Angebote

    Design adc data decoding module. (vivado 2018.2) Input: FCLK,DCLK,DATA_0~DATA_15.(all input signals are LVDS) Output: CLKOUT, DOUT_0 [15:0] ~ DOUT_31 [15:0]. One data path contains two adc signals. The two adc signals are distinguished by FCLK level. I need to decode the adc data into 16-bit wide data and output a total of 32 channels of adc data. The input waveform is shown in the figure. The dif...

    €188 (Avg Bid)
    €188 Gebot i.D.
    7 Angebote

    Vhdl is needed

    €23 (Avg Bid)
    €23 Gebot i.D.
    5 Angebote

    Need help program FPGA to communicate with TI7200 through SPI, and generate 300 and 100 Hz sine waves to drive two electric coils,

    €447 (Avg Bid)
    €447 Gebot i.D.
    14 Angebote
    Diseño FPGAs en VHDL 1 Tag left
    VERIFIZIERT

    Proyecto enfocado al diseño VHDL sobre FPGAS. Desarrollo de código y de bancos de pruebas, verificación del funcionamiento y resolución de algunas cuestiones. Tiene que estar terminado para el día 17 de diciembre. Se adjunta toda la descripción de lo que hay que hacer, así como unas plantillas para las soluciones y algunos bancos de pruebas.

    €29 (Avg Bid)
    €29 Gebot i.D.
    1 Angebote

    Use a Verilog and Do exactly what is on the paper and hand me a report with codes, synthesized diagrams, and a description comparing the different state assignments

    €20 (Avg Bid)
    €20 Gebot i.D.
    6 Angebote
    VHDL questions 2 Stunden left

    I have some VHDL questions which I nedd to be solved .

    €16 (Avg Bid)
    €16 Gebot i.D.
    6 Angebote