FPV Drone 4-in-1 ESC Design

COMPREHENSIVE ENGINEERING SPECIFICATION & LAYOUT GUIDE Project: High-Performance 65A/80A 4-in-1 ESC (AM32) Version: 2.0 (Strict Guidelines for Freelance Layout Engineer) Target Firmware: AM32 (AT32F421) 1. PROJECT OVERVIEW & HARD CONSTRAINTS This document dictates the exact requirements for a 4-in-1 Electronic Speed Controller (ESC) designed for FPV drones. Because the design leverages a 4-layer PCB for a 260A (total) continuous current application, the layout engineer must strictly adhere to the thermal, routing, and stackup guidelines defined below. Deviation will result in thermal failure. Continuous Current: 65A per channel (260A Total) Burst Current: 80A per channel (320A Total) Input Voltage: 3S to 6S LiPo (Max nominal 25.2V, layout must withstand 40V spikes) Dimensions: ~36 x 36 mm (Max outer edge) Mounting Pattern: STRICTLY 30.5 x 30.5 mm (M3 Holes). 20x20mm is forbidden. 2. PCB STACKUP & MANUFACTURING RULES (CRITICAL) The designer must specify these exact parameters in the fabrication notes (Fab Notes) for the manufacturer (e.g., JLCPCB/PCBWay). Layer Count: 4 Layers Copper Weight: Top Layer: 3 oz (Minimum) Inner 1 (GND): 2 oz Inner 2 (Signal/Power): 1 oz or 2 oz Bottom Layer: 3 oz (Minimum) Solder Mask Openings (Bare Copper Expansion): RULE: All main BATT+, main GND, and Phase Output (M1-M4) polygon pours/traces on the Top and Bottom layers MUST NOT be covered by solder mask. Reason: The assembly house will apply thick solder or copper busbars over these exposed areas to increase the cross-sectional current-carrying capacity. If left masked, the 3 oz copper will vaporize at 260A. Thermal Vias: Use an aggressive via stitching grid (0.3mm hole / 0.6mm pad) on all high-current polygons. MOSFET Thermal Pads: Place a minimum of 9 to 12 thermal vias directly inside the Drain (or Source, depending on high/low side) pad of EVERY MOSFET, connecting to the Inner 1 GND plane and Bottom layer for heat dissipation. Do not use thermal reliefs (spokes) on high-current vias; use solid connections. 3. SCHEMATIC & COMPONENT DIRECTIVES 3.1. Microcontrollers (MCU) Part: 4x Artery AT32F421G8U7 (QFN-28). One per channel. Decoupling: Place one 0.1µF and one 1µF ceramic capacitor directly next to the 3.3V pin of EACH MCU. Programming (SWD): You MUST include easily accessible test pads (or through-holes) for SWDIO, SWCLK, 3.3V, and GND for each of the 4 MCUs. Without these, the factory cannot flash the AM32 bootloader. 3.2. Power MOSFETs Part: 24x 40V N-Channel MOSFETs. Package: Strictly 5x6mm (PDFN5x6 / SuperSO8). Do not use 3x3mm. Specs: $R_{DS(on)}$ must be < 0.8 mΩ. (e.g., NCEP40T15G, BSC008N04LS, TPN2R204PL). Snubbers: Leave unpopulated 0603 footprints for RC snubbers (Resistor + Capacitor in series) across the Phase outputs to GND, to allow tuning if ringing occurs. 3.3. Gate Drivers & Bootstrap Part: 4x FD6288Q or NSG2065Q (QFN-24). Bootstrap Capacitors: Must use 1µF or 2.2µF 50V rated X7R ceramic capacitors. Must be placed as physically close to the gate driver pins as possible. 3.4. Current Sensing (Critical Layout Requirement) Amplifier: TI INA186A3 (or INA240). High-side measurement. Shunt Resistor: DO NOT use a single 2512 resistor. USE: Two 0.4 mΩ 2512 footprint resistors in PARALLEL (resulting in 0.2 mΩ total resistance). Scale: Yields ~165A full-scale at 3.3V ADC. Routing (MANDATORY): The traces from the shunt resistors to the INA186 inputs MUST be routed as a Kelvin Connection. Route them as a tightly coupled differential pair directly from the inside center of the shunt pads. Do not tap from the bulk polygon. 3.5. Power Regulators (Buck & LDO) Spike Warning: 6S LiPo with active braking will create >35V voltage spikes. 10V Gate Drive Rail (Buck): Must use a Buck converter rated for minimum 40V input (e.g., TI LMR54406 or equivalent 40V-60V buck). Do not use 24V rated bucks like MP2315. 3.3V Logic Rail (LDO): TLV76733 (or ME6211C33). MUST be powered from the 10V buck output, NOT directly from V_BATT. Input Capacitance: Place at least four 10µF 50V ceramic capacitors (1206 or 1210 size) near the BATT input pads and Buck converter input to handle high-frequency ripple. 3.6. Protection & External Connections TVS Diodes: Place 2x SMCJ24A (or SMF24A) TVS diodes directly at the main V_BATT input pads to clamp inductive spikes. External Capacitor Pads: Provide large through-hole pads at the V_BATT input to allow the end-user to solder a 1000µF 35V Low-ESR electrolytic capacitor. 4. LAYOUT & ROUTING GUIDELINES High Current Polygons (BATT+, GND, Phases): Do not use traces for these. Use massive copper pours (polygons) on Top and Bottom layers. Avoid necking down (bottlenecks) in the BATT+ and GND planes. If a bottleneck is unavoidable, you must stitch it to the opposite layer using multiple vias. Gate Drive Routing (Gate & Source): Traces from the Gate Driver to the MOSFET gates must be short, thick (minimum 15-20 mils), and matched in length as much as possible. Route the Gate and Source return (Phase) traces parallel to each other to minimize loop inductance. Signal Routing (DShot/Telemetry): Route DShot signal lines on Inner 2. KEEP AWAY from the switching nodes (Phase outputs, Buck converter inductor) to prevent PWM noise from causing desyncs. Ensure a solid, unbroken GND reference plane (Inner 1) exists directly above/below all DShot signal traces. Motor and Battery Pads: Motor output pads must be large enough to easily solder 14AWG / 16AWG wires (Minimum ~5x5mm exposed copper). Battery input pads must be exceptionally large, preferably mirrored on both Top and Bottom layers and heavily stitched with vias, to support 10AWG / 12AWG wire. 5. CONNECTOR PINOUT (8-Pin JST-SH 1.0mm) Place the connector near the edge of the board, away from the BATT+ input to minimize noise. V_BATT (Battery voltage to FC) GND CURR (Analog current sensor output from INA) TELEM (ESC Telemetry - ESC TX to FC RX) M1 (DShot Channel 1) M2 (DShot Channel 2) M3 (DShot Channel 3) M4 (DShot Channel 4) 6. DELIVERABLES REQUIRED FROM FREELANCER Upon completion, the layout engineer must provide: Native Source Files (Altium, KiCad, or EasyEDA format). Gerber Files (RS-274X or X2 format) including Drill files. BOM (Bill of Materials) with exact manufacturer part numbers. CPL (Component Placement List / Pick & Place file) for assembly. 3D STEP Model of the completed PCBA. A brief DRC Report proving 0 errors.

Project ID: 40605990