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Custom Verilog design

13 Freelancer bieten im Durchschnitt $26 für diesen Job

ahmedmohamed85

Dear sir I have more than 10 years experience in digital design using verilog please check my profile also please message me so that we can discuss best regards

$30 USD in 1 Tag
(310 Bewertungen)
7.6
loi09dt1

A proposal has not yet been provided

$30 USD in 3 Tagen
(130 Bewertungen)
6.6
raulbehl

Hello! I am an experienced Engineer and have been helping out many on this platform. It would be great if I could help you out. Thank you! Relevant Skills and Experience Verilog and Digital Design - 4+ years Proposed Mehr

$25 USD in 1 Tag
(54 Bewertungen)
5.7
sajjadahmed19

Hi I know about verilog Relevant Skills and Experience design Proposed Milestones $25 USD - verilog

$25 USD in 1 Tag
(37 Bewertungen)
5.5
SqUa11

Hello, My name is Mohamed. I have checked your project description about building a custom Verilog design. I can guarantee to deliver high quality code Relevant Skills and Experience 5 years experience in digital desi Mehr

$30 USD in 1 Tag
(70 Bewertungen)
5.3
viseros

hi, please send me the details of your project. Relevant Skills and Experience verilog Proposed Milestones $25 USD - complete

$25 USD in 1 Tag
(3 Bewertungen)
2.9
sourindu

A proposal has not yet been provided

$35 USD in 4 Tagen
(1 Bewertung)
2.3
filip992

Hi, share details so I could give precise estimations. BR Relevant Skills and Experience I have 2 y working experience in Verilog/VHDL, I am more familiar with Altera FPGAs, worked in ASIC design mostly. Familiar with Mehr

$25 USD in 1 Tag
(1 Bewertung)
1.1
$25 USD in 1 Tag
(1 Bewertung)
0.0
graphicsinsect

please visit our portfolio link [url removed, login to view] Relevant Skills and Experience please visit our portfolio link [url removed, login to view] Proposed Milestones $15 Mehr

$15 USD in 0 Tagen
(0 Bewertungen)
0.0
ahmednawaz803

I have done many projects in verilog, also I have worked on FPGA in Final Year Project. So this bid means for me! Relevant Skills and Experience Verilog HDL, Proposed Milestones $1 USD - Understanding the Project $12 Mehr

$19 USD in 1 Tag
(0 Bewertungen)
0.0
Tbtran

8 years in asic/fpga design field. I have some free time now .

$25 USD in 1 Tag
(0 Bewertungen)
0.0
jayesh1686

I would like to get the design specs. Relevant Skills and Experience VHDL/Verilog Proposed Milestones $25 USD - Complete RTL code

$25 USD in 5 Tagen
(0 Bewertungen)
0.0