Digital VLSI / ASIC Project – Verilog, Synthesis, Gate-Level Simulation & Power Analysis (Cadence) -- 2

@Mahihassi

With over a decade of experience in electrical engineering, digital design and ASIC flows with Cadence tools, I assure you that your Digital VLSI/ASIC project is in safe hands. My proficiencies extend from RTL design to power estimation, and my record speaks volumes for my abilities to follow through on projects. Your project’s use of Verilog, Synthesis, Gate-Level Simulation and Power Analysis is well within my area of expertise. Furthermore, I have a Master's in Embedded Systems which has equipped me with an enviable skill-set adaptable across multiple disciplines. Throughout my career, I have successfully developed high-performance digital systems using Verilog/VHDL— a task that will be fundamental to your project. Additionally, my knowledge of FPGA development has enabled me to deliver optimal signal processing and hardware acceleration. Beyond VLSI/ASIC, I am also experienced in firmware development, IoT product engineering and more - a thorough understanding of the complete product development workflow. From concept to prototype to final product, I assure you unrivaled dedication and proficiency at every step involved. Let’s make your project a success together!

@anilptk

Hi, I am an experienced Digital VLSI/ASIC engineer with a strong background in RTL design, synthesis, gate-level simulation, and power estimation using Cadence tools. I have successfully completed similar projects, ensuring adherence to standard ASIC front-end flows. I am proficient in Verilog and VHDL, and I possess a solid understanding of very-large-scale integration (VLSI) principles. My approach is detail-oriented, ensuring that all aspects of the project are executed efficiently and accurately, leveraging the provided templates and documentation. I am committed to delivering high-quality results within the specified timeline. I look forward to the opportunity to contribute to your project and help achieve your goals. Thank you for considering my proposal.

@peconsultation

Good day, I’m a Digital VLSI/ASIC engineer with hands-on experience executing complete RTL-to-power analysis flows using Cadence tools, including RTL development, synthesis, gate-level simulation, and accurate power estimation. I’m comfortable working within pre-defined project structures, templates, and documentation, ensuring strict adherence to your existing methodology while maintaining clean, verifiable results. My background includes timing-aware synthesis, switching activity generation, power analysis correlation, and clear reporting suitable for technical review. I work efficiently, communicate clearly, and focus on correctness rather than assumptions, making me well-suited to deliver a reliable end-to-end front-end ASIC flow aligned with your project requirements.

@yanatejaip5s

I used to work with Cadence Genus to do Logic Synthesis with Skywater 130nm Library as well as do gate level simulation with and without sdf annotation.

@temciucv

Hello Nate S., We would like to grab this opportunity and will work till you get 100% satisfied with our work. We are an expert team which have many years of experience on Engineering, Electronics, Verilog / VHDL, Electrical Engineering, Very-large-scale integration (VLSI) Lets connect in chat so that We discuss further. Thank You

@adily1

Hi There, I understand you're seeking an experienced Digital VLSI / ASIC engineer for an end-to-end RTL-to-power analysis project using Cadence tools. My expertise aligns perfectly with your requirements, allowing me to ensure seamless execution of the ASIC front-end flow from RTL design through to power estimation. I am Adil Yousuf, a VLSI engineer with over 6 years of experience in Engineering, Electronics, Verilog/VHDL, and Electrical Engineering. My proficiency in digital design and power analysis will facilitate delivering precise results for your project swiftly. You can review my relevant work and previous projects through my portfolio here: https://www.freelancer.com/u/adily1 I look forward to the opportunity to collaborate and contribute to your project’s success. Thanks, Regard, Adil Yousuf

@muhibwatni2

Hi, THIS BID IS NOT AI GENERATED BID. I read your job post and understand you need a precise execution of the RTL-to-Power flow using the Cadence toolchain. I can help by performing the synthesis in Genus, verifying the netlist via gate-level simulation (GLS), and generating high-accuracy power reports using Joules or Innovus based on your specific activity (SAIF/VCD) files. I am an experienced VLSI engineer proficient in mapping RTL to standard cell libraries while meeting timing and area constraints. I will strictly follow your provided templates to ensure the project structure remains consistent, delivering optimized Verilog netlists, SDC constraints, and detailed power breakdowns (leakage, internal, and switching power). My focus is on ensuring the correlation between your simulation activity and the final power estimation is technically sound and meets your documentation standards. Regards, WM

@jhaira4

I’m an electrical engineer with knowledge on the topic able to perform this work pretty smoothly. Please let me know

@kenb452

Hi there, I am an experienced Digital VLSI/ASIC engineer with a strong background in RTL design, synthesis, gate-level simulation, and power estimation using Cadence tools. I am confident in completing the end-to-end RTL-to-power analysis project, ensuring high-quality results. With the provided project structure, templates, and documentation, I can efficiently deliver the required output. I look forward to contributing to the success of your project. Best regards, Kenneth

@naveenc24

Hello mam, I am Naveen Chakali, an FPGA/ASIC RTL Design Engineer with hands-on experience in communication systems, custom IP design, and FPGA-based prototyping. I have worked on QPSK modulators, DVB-S2 PHY modules, HDMI/VGA display systems, AXI-based IPs, and SoC (Zynq) integrations. I specialize in: Verilog/VHDL/SystemVerilog RTL design Vivado/Vitis, ModelSim, MATLAB/Simulink (HDL Coder) AXI-Stream interfaces, PS–PL, DMA Testbench development, simulation, ILA debugging Communication protocol IPs (UART/SPI/I2C) I can deliver end-to-end FPGA development: design → simulation → synthesis → implementation → hardware testing.

@vtlkanase

Hello, I am an experienced Digital VLSI / ASIC engineer with hands-on expertise in Verilog RTL design, synthesis, gate-level simulation, power analysis, and physical design using Cadence tools. I can deliver: RTL verification / clean Verilog Synthesis using Cadence Genus Gate-level simulation (NCSim ) Power estimation using Cadence Genus Area, timing, and power reports as per provided templates I am familiar with standard ASIC front-end RTL-to-power flow and can follow your project structure and documentation. Ready to start immediately.