Experienced VLSI Design Trainer Required- Vietnam

@MQamar123

As a veteran in software development for over 7 years, my background allows me to easily adapt to new technologies. I'm particularly drawn to this VLSI Design Trainer position as it provides a challenge in blending my programming skills and your expectations. This unique role demands that you impart skills on a wide range of EDA tools such as Yosys, OpenROAD, Synopsys PrimeTime, Magic, and Netgen which aligns well with my history of technological versatility. Along with prior experience in training the batch sizes equivalent to 30+ students/interns like yours, I'm confident that I am the best fit for this job. Furthermore, your description mentions the importance of efficient flow automation through scripting and strict adherence to timing analysis principles. My fluency in Python which extends to automation, parsing, and report generation; along with noteworthy knowledge in TCL for EDA scripting; and Shell/Bash/Perl for flow automation and log parsing respectively would be invaluable assets in carrying out this role effectively.

@ashinnd84

Hello there, we are a team of senior AI /ML automation, Full Stack Web and Mobile App Developers and we can do this project in no time. Thanks Ashish Kumar.

@alluankit01

Hi, I can design and deliver a complete hands-on VLSI training program covering the full RTL-to-GDSII flow, with structured lessons, practical labs, assessments, and intern progress tracking. The best approach is to begin with Verilog/SystemVerilog RTL design and UVM verification, then progress through Yosys synthesis, SDC constraints, OpenSTA timing analysis, OpenROAD/OpenLane physical design, CTS, routing, and DRC/LVS using Magic and Netgen. I’ll also include AXI4, SPI, I2C, UART, Git, and scripting with Python, TCL, Bash, and Perl. I’m comfortable with RTL design, synthesis, STA, physical design, verification, Sky130 PDK, LEF/DEF, standard-cell libraries, timing closure, protocol testbenches, and EDA workflow automation. Deliverables will include: * Complete RTL-to-GDS curriculum * Daily session and lab plans * Verilog/SystemVerilog exercises * UVM verification labs * Yosys/OpenROAD/OpenSTA training * Magic/Netgen DRC and LVS * Sky130-based mini-project * Assignments and assessments * Attendance and progress reports * Tool setup and documentation support I’ll focus on practical, industry-oriented training that helps interns complete a full chip-design flow independently. Best regards Ankit

@irfanui

Hi, I reviewed your project: Experienced VLSI Design Trainer Required. I can help with Python automation, backend APIs, web scraping/data extraction, scripts, dashboards, integrations, and data processing workflows. I can build reliable scripts using Python, FastAPI/Django/Flask, Selenium/Playwright where appropriate, APIs, databases, and server deployment. Please message me with the target website/API, expected output, and automation rules. Portfolio: https://www.freelancer.com/u/irfanui Regards, Mohammad 4th Dimension Partners

@caodung171800

Dear Client, I hope this message finds you well. I came across your VLSI Design Trainer opportunity and I am genuinely excited. I have strong hands-on experience in RTL-to-GDSII flow with open-source tools like Yosys, OpenROAD, and Sky130 PDK, and I would love to mentor your engineering interns. What is the target? You need an experienced trainer to deliver structured VLSI training covering RTL design, synthesis, physical design, STA, DRC/LVS, industry protocols, and scripting—ensuring interns are industry-ready upon program completion. Core skills: Verilog / SystemVerilog / UVM Yosys / OpenROAD / OpenSTA Sky130 PDK / Magic / Netgen Python / TCL / Shell Scripting AXI4 / SPI / I2C / UART Protocols How I solve & deliver: Design comprehensive curriculum with hands-on labs. Conduct sessions on RTL-to-GDS flow using open-source tools. Guide interns through synthesis, PnR, STA, and sign-off. Evaluate progress through assignments and mini-projects. Maintain session plans and progress reports. Thank you for your time. I am confident I can deliver high-quality, industry-relevant training. Best Regards

@mundadiya

With over 5 years of VLSI design experience, I'm well-equipped to mentor engineering interns on RTL-to-GDSII design flows using industry-standard EDA tools. My past projects include creating hands-on labs with Yosys and Verilog coding. How can we tailor the curriculum to ensure interns grasp STA concepts effectively? Regards, mundadiya