Verification IP development for AXI Protocol using system Verilog

Hello! Please check my profile and reviews to know a bit about me and my work. Hope you would contact to discuss further. Thank you! Relevant Skills and Experience Verilog - 3+ years AXI Protocol - 2+ years SV/UVM - 2+ years Proposed Milestones ₹13888 INR - As per the discussion

I'll create VIP for AXI with master and slave modes in constrained verification random environment. If UVM is ok, i'll base that testbenc on UVM. Relevant Skills and Experience Expert System verilog knowledege, many years of verification experience Proposed Milestones ₹3000 INR - Create all components of testbench including drivers, monitors, scoreboard, environment ₹2000 INR - Add sequences and create basic tests, to make sure master and slave are working correctly ₹2777 INR - Add random sequences, create more tests, also coverage and assertions will be added. Question: Is it ok to base this testbench on UVM SV?

I would be able to finish this proficiently as I have know this protocol well and my current project also involves this project. Relevant Skills and Experience I am working as a Sr. ASIC Verification Engineer in one of the core companies of this domain (eInfochips) since past 4 years. I have worked on protocols like AXI, AHB, APB, SPI, I2C, PCIe, Ethernet. Proposed Milestones ₹12222 INR - Complete VIP model with configurable master and slave. Only the basic question that we need to follow the standard Amba AXI Specs only, right?