H.264/H.265 decoder

Dear sir I have more than 10 years experience in digital systems design using vhdl and verilog, please check my profile, also please message me so that We can discuss Best regards

Hello , how are you? Hope all is fine ! Regarding your project I have long experience with FPGA and VHDL . I work with both intel and Xilinx FPGAs , SoC and SOPC.I use Quartus II and Vivado IDEs accordingly. I test timing compliance through timing analysis . I deliver tested , neat and well-commented code that can be reused or modified for future development. Regarding the Video CODEC part , I have worked before on H.264 standard and I implemented soft decoder (C++ code just for testing as part of R&D) and I managed to implement the blocks (having understood the algorithm with the aid of third-party tools) as VHDL code. I can show how how far I have gone . More to be discussed once you contact me . BR, M.T.

Hi, I'm an electronic engineer with more than 5 years of experience in Digital system designing. Currently I'm working for leading EDA company in silicon fabrication and I'm very good at Verilog designing. Also I have IEEE publication on ASIC development as well. I'm looking forward to hear back from you with more information on the specification. Thank you Anusha

I'm an Electronics and Telecommunications Engineer having a master degree in EE. I have experience in design and implementation of electronics projects. In a related work I have wrote a VHDL code H264 video compression and decompression. I offer a clean shot solution for your project, however we need to talk more in detail. * the price and delivery time of project is based on default values of website and may change after more negotiation. ** I can only provide VHDL code, however using appropriate software (ex. cadence) you can convert this code to ASIC layout automatically.

I am in hardware asic designer working on algorithms and packet checking for firewall asics in Silicon valley. Extensive knowledge designing, debugging, running simulations and closing timing for ASIC design flow. Familiar with compile, sim tools and lint tools. Guaranteed 100% completion rate on time.