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DVLSI project 'ASIC design of face detection using haar wavelet'.

2 Freelancer bieten im Durchschnitt ₹21250 für diesen Job

Ahmed8033

Hi, i have seen your project, i have experience in Verilog coding, I have also experience with Image processing.

₹12500 INR in 7 Tagen
(1 Bewertung)
0.3
FSFH

Design Engineer with Experience in large scale complex systems development with practicing in Verilog, SystemVerilog, Porgramming Firmware, C, C++. Let's Discuss further.

₹30000 INR in 30 Tagen
(0 Bewertungen)
0.0