FPGA implementation of a data structure

Data communication protocol to receive data in FPGA using data structure to synchronise between receiver and sender. Currently using same approach in other projects. Relevant Skills and Experience Has experience 4 years in VHDL Zynq and Spartan 3e. Proposed Milestones $250 USD - IP core in VHDL for the design alongwith test benches

Dear sir I have more than10 years experience in digital design using fpga, please check my profile also please message me so that we can discuss best regards

A proposal has not yet been provided

I have over a decade of experience in the ASIC design field, I look forward to hearing the details of the project. Relevant Skills and Experience 10+ years of experience in ASIC design. Proposed Milestones $555 USD - delivery of verilog code. Note: This is a tentative bid and will be updated, Post our discussion on the exact algorithm etc

A proposal has not yet been provided

I am an expert in FPGA design for both Xilinx and Altera Relevant Skills and Experience VHDL/Verilog Proposed Milestones $370 USD - Complete Working code

please contact me for direct discussion on project, if you are interested. Thanks, Hayk Relevant Skills and Experience usb3, usb2, verilog, simulation, CDC analysis, synthesis, fpga-prototyping Proposed Milestones $555 USD - project

Selamlar, tam olarak istediginiz nedir ? Block RAM kullanmak istiyorsunuz anladigim kadariyla, yani veri miktari kucuk. DDR vs baglama gibi bir ister var mi ? Yazilimla haberlesme kanali ne sekilde olacak ? PCI express uzerinden mi yoksa UART/SPI gibi bir peripheralle mi istiyorsunuz ? Hangi FPGA targetlenecek ? Detayli goruselim lutfen, tesekkurler ! Relevant Skills and Experience C, C++, Embedded Systems, Digital Design, VHDL, FPGA Proposed Milestones $700 USD - Sentezlenebilir VHDL kodu, testbenchleriyle birlikte. Gerekirse driveri de eklenir.