Fix Cadence XOR gate schematic
$10-30 USD
Bezahlt bei Lieferung
I have a very simple Cadence schematic and layout I have designed of an XOR gate. For some reason the nest lists do not match in the LVS check. I cannot figure out this simple task because I am new to the process.
The layout cannot change but corrections can be applied and the entire schematic can change to make the proper corrections to match the layout.
Projekt-ID: #18000481
Über das Projekt
7 Freelancer bieten im Durchschnitt $25 für diesen Job
Am full-time freelancer expert in Electrical & Electronic Circuit Designing & Simulation, PCB Designing, Consultancy of different types of Electrical & Electronic Problem. I can write Fix Cadence XOR gate schematic, I Mehr
Hi, I am an IC Mask Layout Design Engineer. I can fix your problem in less than 1 hour. I have experience to design layout in TSMC/GF/XFAB/NCSU PDK @7/16/22/130/180nm node. I have Cadence Virtuoso also. I think yo Mehr
Hello, I've read your job description and I can help you with this task because I've 5+ years of experience using Cadence Virtuoso for all layers of VLSI design. I've faced this exact issue myself for there is a reaso Mehr
Hello, I am an electronics engineer having experience in design using cadence virtuoso for more than 5 years.
I can design this Relevant Skills and Experience I am electronic engineer , I can design xor gate for ypu
