Cache Question

(a) Consider a two-way set associative cache with four-word blocks that stores a maximum of 32 words. Show the hits and misses and final cache contents for the following series of address references given as word addresses: 1, 4, 8, 5, 20, 21, 17, 15, 19, 56, 9, 33, 21, 11, 4, 43, 5, 6, 9, 11, 17. Assume LRU replacement. (b) Assume that this cache architecture uses one bit for Valid (V), one bit for Dirty (D), two bits to indicate Number of References (R), and a 32-bit memory address. Calculate the total size of this cache in bits. (c) Consider a direct-mapped cache with eight-word blocks that stores a maximum of 32 words. Show the hits and misses and final cache contents for the following series of address references given as word addresses: 1, 4, 8, 5, 20, 21, 17, 15, 19, 56, 9, 33, 21, 11, 4, 43, 5, 6, 9, 11, 17. Assume LRU replacement. (d) Assume that this cache architecture uses one bit for Valid (V), one bit for Dirty (D), two bits to indicate Number of References (R), and a 32-bit memory address. Calculate the total size of this cache in bits. ## Deliverables ASCII TEXT ## Platform ASCII TEXT