Design and implementation of SPI interface
₹37500-75000 INR
Bezahlt bei Lieferung
To write the VHDL code for the behavioral specification of the SPI Slave and Master Interface and to implement the write and read operation on SRAM using CPLD board.
Projekt-ID: #8340621
Über das Projekt
21 Freelancer bieten im Durchschnitt ₹48849 für diesen Job
Dear sir I have more than 8 years experience in digital design using verilog and vhdl please check my profile also please message me so that we can discuss
I would like to bid this job because I am really suitable for job description: First: I am an Electronics engineer who is very familiar withVHDL/Verilog. In fact, I have done so many project of VHDL/Verilog(Karatsuba Mehr
Dear Sir, I'm the Verilog/ VHDL expert and the best VHDL freelancer on this site. please contact me and we can discuss more. Thanks. Loi
Hi I have total 10+ years of experinece , I have worked and designed SPI based master slave for commercial IPs as well , I have xilinx based FPGA board to test, I am committed to provide best quality work. I unders Mehr
I am an engineering graduate with experience in electronics and control systems. I seek a long term career within an organization that challenges me intellectually and professionally. I have a propensity to work in cha Mehr
dear sir, we are team of highly experienced professionals. we work in different embedded technology like microcontrollers, fpga, etc. we are interested in this project pls reply.
Dear sir, I believe I am your right candidate to collaborate with you in this project. I'm an senior electronic engineer with more than nine years of experience working with FPGAs, HDLs, Digital Design, DSP, embe Mehr
I have been working with verilog more then one year. I have some ended projects on verilog, which work in hardware, not only in simulator. And a have been working with VHDL more then 3 years.
Am recently working on fpga based vlsi design project as my post graduate project & have enough knowledge on this field.
I have done extensive Verilog Design and SPI can be done very well. I am already familiar and expert with VhDL and Verilog.
I have been designing memories with SPI interfaces the past thee years. My last major project was a DDR2 memory with a SPI interface for configuration and memory access. I just completed 5 testchips with SPI interfac Mehr
4+ years exp in FPGA/CPLD Design. Xilinx certified Design Engineer. Expertise in FPGA based Power Processor (PPC) and Microblaze. Language expertise in VHDL,Verilog and System Verilog. Process based code structure. Mehr
I,ve designed and used SPI Interfacing in some project using FPGAs. Also I used Zynq SPI Interface for Write or Read.
I worked on SPI protocol design earlier and having good hands on experience. I will be well suited for this. Looking forward
I already wrote SPI protocol to the FPGA VHDL language and communication between MASTER and SLAVE I am well acquainted with this protocol.
