develop a CAD tool that can read in the “logical RAMs” in each circuit of a benchmark set, and output a set of “physical RAMs” that can implement the logical RAMs for each circuit

You will develop a CAD tool that can read in the “logical RAMs” in each circuit of a benchmark set, and output a set of “physical RAMs” that can implement the logical RAMs for each circuit. Your tool should be able to target FPGAs with up to 3 types of physical RAMs (which may be 3 different block RAMs, or 2 block RAMs and “LUTRAM” created by using a logic block as RAM). Your CAD tool should attempt to find a solution that minimizes the area of the FPGA needed to fit each benchmark circuit.

C Programmierung C++ Programmierung CAD/CAM FPGA

Projekt-ID: #18132763

Über das Projekt