Digital class

Provide detailed answers to the following: • Show the bit configuration that represents the decimal number 255 in (a) Binary, (b) Binary Coded Decimal (BCD), (c) ASCII, (d) ASCII with odd parity. • A 2-bit comparator compares two 2-bit words, A and B, and assets outputs indicating whether the decimal equivalent of word A is less than, greater than or equal to that of word B. K-map method can be used to derive the minimized equations to describe the behavior of the comparator and Verilog module can be written to test the working of the comparator. Complete the following: o Derive minimized equations for the comparator outputs - A less than B, A equal to B, and A greater than B. Draw logic diagram. o Write and test the Verilog Module for this comparator. Provide detailed answers to the following: 1. How will you use a 3x8 decoder to build a 4x16 decoder? Draw a schematic diagram and explain your solution. 2. How will you use a 4x1 multiplexer to build a 16x1 multiplexer? Draw a schematic diagram and explain your solution. 3. Implement the following Boolean function with a multiplexer: (a) F(A, B, C, D) = ∑(0, 2, 5, 8, 10, 14) (b) F(A, B, C, D) = Π(2, 6, 11) Provide detailed answers to the following: 1. Design a combinational circuit with three inputs, x, y, and z, and three outputs, A, B, and C. When the binary input is 0, 1, 2, or 3, the binary output is one greater than the input. When the binary input is 4, 5, 6, or 7, the binary output is two less than the input. Your solution must include the following: (a) Truth table (b) K-map minimization (c) Simplified equation and logic diagram (d) Simulation using Verilog of the logic circuit in step (c). 2. A majority circuit is a combinational circuit whose output is equal to 1 if the input variables have more 1’s than 0’s. The output is 0 otherwise. (a) Design a 3-input majority circuit by finding the circuit’s truth table, Boolean equation, and a logic diagram. (b) Write and verify a Verilog gate-level model of the circuit. 3. Implement a full adder with two 4x1 multiplexers.