Matrix Multiplier Project-VHDL

The project must meet certain requirements. Firstly the project (VHDL design and VHDL testbench must be completely free of syntax errors. The VHDL project must synthesise with no problems, such as non-synthesisable code, latch inferred and multi-driver. Must show correct results from behavioural simulation and post-route simulation, in which the post-route delay can be observed. Must have the best coding quality with highest efficiency with the most effective hardware resource consumed and efficient processing speed achieved. Must include adequate notes on each section or line indicating processes and stages of code , what is does and how it works; and what they are used for and how they are used. A report is to be written on the project. Needs to be able to implement using advanced signal processing algorithms for an FPGA based embedded system. VHDL should be used to design a matrix multiplier core that will b used on a Xilinx FPGA device. Use Xilinx ISE Design Suite 13.4 and Mentor Graphics ModelSim SE 10.1!!!!