PID Controller in VHDL or Verilog

Development of a PID controller in HDL (VHLD or Verilog) for Xilinx FPGA Spartan 6. The development shall be with WEBPACK Xilinx. The? implemented PID shall not be larger than 400 slices. The The PID shall be developed? at 32bits precision, and intermendiate values extended at 48 bits and shall include: • command ??" The setpoint, as commanded. • feedback ??" as measured by a feedback device. • output ??" The elaborated output command that is the control signal . • error ??" is command minus feedback. • enable ??" A bit enabling the PID. If false, all integrators are reset, and the output is forced to zero. If true, the loop operates normally. The PID gains, limits, and other ’tunable’ features of the loop are implemented as parameters? at 32 bits. •? Pgain ??" Proportional gain •? Igain ??" Integral gain •? Dgain ??" Derivative gain •? bias ??" Constant offset on output •? FF0 ??" Zeroth order feedforward - output proportional to command. •? FF1 ??" First order feedforward - output proportional to derivative of command. •? FF2 ??" Second order feedforward - output proportional to 2nd derivative of command. •? deadband ??" Amount of error that will be ignored •? maxerror ??" Limit on error •? maxerrorI ??" Limit on error integrator •? maxerrorD ??" Limit on error derivative •? maxcmdD ??" Limit on command derivative •? maxcmdDD ??" Limit on command 2nd derivative •? maxoutput ??" Limit on output value All of the max limits are implemented such that if the parameter value is zero, there is no limit. Four additional parameters shall be visible ( exported): •? errorI ??" Integral of error. •? errorD ??" Derivative of error. •? commandD ??" Derivative of the command. •? commandDD ??" 2nd derivative of the command. ## Deliverables 1) All deliverables will be considered "work made for hire" under U.S. Copyright law. Employer will receive exclusive and complete copyrights to all work purchased. (No 3rd party components unless all copyright ramifications are explained AND AGREED TO by the employer on the site per the worker's Worker Legal Agreement). 2) Source code of the PID with comments 3) Simulation files and test files 4) Synthesis report of WEBPACK ## Platform Spartan 6 Xilinx FPGA