Fpga Jobs

Hi everyone. I'm working right now with my project about direction-of-arrival estimation. I need to implement it in FPGA using Verilog. One of the steps in my algorithm is to compute for the eigenvalues and eigenvectors of my correlation matrix. I have already computed for the correlation matrix and simulate it in modelsim. Next step is to do eigendecomposition and compute for the direction of the signal and that's my problem right now. Can anyone help? I have already dealt with somebody about this but he just abandoned me leaving the project unfinished. So I need someone who has really the knowledge about this topic. Thanks...

For people who are used to Altium Designer, there is a PCB design example featuring a Xilinx FPGA SPARTAN 3A DSP daughter board. I would like to: 1- make that board a stand-alone board so that I can design a product based on it. 2- or if you are selling a PCB Design featuring a Xilinx FPGA we can talk about it.

I need a voice recorder and play recorded data ; in this project Altera cyclone 2 EP2C70F896C6N fpga will use Start and stop the recording. play recordind data

Hi, I am working on hardware implementation of Elliptic Curve Cryptography on FPGA. So I need help related to it. Do you have any idea related to cryptography,Galois Field,Finite State machines? Please let me know as soon as possible.

Hello, i am looking for someone who can write a custom firmware and miner for some 250mhz FPGA's which will be in a huge cluster, which communicate by VME. I have documentation on the devices and vcr files. If you are familiar in this field and are familiar with Bitcoin please feel free to contact me to discuss this further. Thank you for your time. we look forward to working with you.

I am looking for a engineer who would be capable of designing and building a prototype FPGA lite coin mining unit. I'm looking to have the implementation described below developed for the Quad-Spartan 6 LX150 :ztex_boards:ztex_fpga_boards:litcoin_mining_on_fpga A new bitstream will need to be created as well as software. I have 6 quad boards that I wish to have working in parallel. I can supply remote access, as well as the platform needed to perform work. Anyone willing to experiment with this challenge please contact me.

I need a SATA Host controller for Kintex-7. There are some open source controllers available. The work involves porting them to Kintex-7.

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I am looking for an FPGA enginner with specific knowledge in ZEDBOARD or any other ZYNQ platform. The engineer must have good experience with ZYNQ and PL-PS communication using AXI. The task is for few days only and is urgent! Additional information in PM. Please apply only if you're able to work in the next few days and have sufficient experience with ZYNQ. Thank you

FPGA VHDL project FPGA VHDL project FPGA VHDL project FPGA VHDL project FPGA VHDL project FPGA VHDL project

I already have FPGA hard ware (XESS XSA-3S1000 FPGA board mounted on an XST-4 board). Also Already have separate program of USB ip core and RS232 ip core. The job is to write a VHDL code or modify existing ip core to combine this two core to become one program of USB to RS232 converter. Help me to trouble shoot till USB to RS232 converter work. Explain how the program work.

We are searching for an electronic specialist, who has experience in designing ASIC or FPGA Hardware. The project is a bitcoin miner in usb stick format The only condition is that the USB Bitcoin Miner must be produced at low cost.

My group is looking for an HW developer that can design and produce a 3000GH/s Bitcoin miner. More detailes on the protocol to be implemented can be find at "";. For those who need more directions I suggest the following - 1) Open an account at ""; 2) Read the instructions on ""; 3) Evaluate your hardware using the GUI miner, or any software for your hardware miner you can design. There is an open source from the software miner at ""; Hope it helps. DSPs that might be more relevant for the project -

Hi everyone. I'm working right now with my thesis about direction-of-arrival estimation. I need to implement it in FPGA using Verilog. One of the steps in my algorithm is to compute for the eigenvalues and eigenvectors of my correlation matrix. I have already computed for the correlation matrix and simulate it in modelsim. Next step is to do eigendecomposition and compute for the direction if the signal and that's my problem right now. Can anyone help? Thanks...

design a digital circuit using VHDL for spartan_ 6 LX9 microboard ,, And explain the project ,,,,,,,

FPGA Verilog design We have a Spartan 3E FPGA PCB which takes in 8 channels of analog signals and sends them to a laptop using 10M ethernet UDP. The signalling is all done in the FPGA including ARP and UDP layers. A static IP address is used. Even the front end signal generation and reception is done by bitbashing in the FPGA. There are also other timing controls set up from the laptop, also via UDP. These include serial DACs and ADCs and other internal controls. We will design and build the PCB, load the code and test it. Task: Identification of a suitable 100M Phy device for production hardware. Port of the FPGA’s ARP and UDP layers to the new Phy interface. The current FPGA code in written in Verilog. Change the timin...

its a digital design requires Fpga and vhdl project details will be made available in person.

Hi everyone. I'm working right now with my thesis about direction-of-arrival estimation. I need to implement it in FPGA using Verilog. One of the steps in my algorithm is to compute for the eigenvalues and eigenvectors of my correlation matrix. I have already computed for the correlation matrix and simulate it in modelsim. Next step is to do eigendecomposition and that's my problem right now. Can anyone help? Thanks...

its a digital design requires Fpga and vhdl project details will be made available in person.

Hi developers, I need help in doing my project of programming with FPGA. If you have experience in this field, please contact me. Thanx

Hi developers, I need help in doing my project of programming with FPGA. If you have experience in this field, please contact me. Thanx

which will run on spartan3 FPGA and show output on LCD.

...lastLogs:x] componentsJoinedByString:@”n”]; // last x logs - x is unsigned integer 4. we need to allow controlling the speed to present during the training the difference in power consumption for mobile apps so we need something like: 
 = 20000; // 20 kH/s 
or
 = 0; // no limitation That’s all, no extra features like using GPU, FPGA, only CPU. No overclocking, no temperature checker. No reconnection - if the internet or pool is inaccessible just stop the miner and throw an exception. Only the user interface coded by us (can be provided, but is so simple that you can recreate in 5 minutes) has to be in Objective-C, and it needs to communicate with Miner using Objective-C, the rest can be either in Objective-C or c/c++.

Using Code Composer Studio v5 and TI's Starterware. The Cortex A8 needs to be set up to access an external FPGA using 16-bit multiplexed address/data. The aim is to access the FPGA internal memory over the GPMC bus from SYS/BIOS tasks (reading or writing values). The memory is quite small - 16K addresses of 16-bit values This is for the BB not BBB, because I don't have the JTAG programmer. Submission is to use Texas Instruments' Code Composer v5 (can be freely downloaded and evaluated) with Starterware and SYS/BIOS. Submission must be the entire project, with include paths to the standard install directories (starting c:ti ). Comments and code names written in English

The aim of this project is to des...implement a digital circuit that enables to find the minterms of a given Karnaugh map. You should design the circuit by using Verilog and implement on the FPGA boards in the laboratory. You will be given the truth table and you will give the information on the truth table as inputs to the system. Your circuit will determine minterms of the system as sum of products or product of sums. There will be another control on your circuit that will determine the type of function. You will also implement the same problem by using NAND gates only and give the function. The circuit will give outputs and you will use seven segment displays on the Xilinx FPGA board to represent the outputs. Your outputs on the screen will be the letters that repr...

The aim of this project is to des...implement a digital circuit that enables to find the minterms of a given Karnaugh map. You should design the circuit by using Verilog and implement on the FPGA boards in the laboratory. You will be given the truth table and you will give the information on the truth table as inputs to the system. Your circuit will determine minterms of the system as sum of products or product of sums. There will be another control on your circuit that will determine the type of function. You will also implement the same problem by using NAND gates only and give the function. The circuit will give outputs and you will use seven segment displays on the Xilinx FPGA board to represent the outputs. Your outputs on the screen will be the letters that repr...

The aim of this project is to design ...digital circuit that enables to find the minterms of a given Karnaugh map. You should design the circuit by using Verilog and implement on the FPGA boards in the laboratory. You will be given the truth table and you will give the information on the truth table as inputs to the system. Your circuit will determine minterms of the system as sum of products or product of sums. There will be another control on your circuit that will determine the type of function. You will also implement the same problem by using NAND gates only and give the function. The circuit will give outputs and you will use seven segment displays on the Xilinx FPGA board to represent the outputs. Your outputs on the screen will be the letters that repr...

Need an efficient GUI and FPGA and or RT based cRIO compatible program to control four hydraulic actuators either in stroke or load control mode. The code should be modular and scalable. Meant for an 8 slot chassis that gives the user a means to configure hardware channels in the fpga dynamically as per the physical configuration. Details will be shared later.

I am looking for engineers who have experience with Bitcoin or Litecoin development. We are interested in developing a FPGA / ASIC for Bitcoin and developing a better GPU with lower power rating and higher calculations. If you have the knowledge in these areas please contact me. Rob Fross

I have two jobs. The first one is basic. I need to create the files necessary to manufacture pcb from files attached. This is an fpga mining board designed for hashing using Spartan6 chipset. If there is a way to improve the design while keeping the cost down then that is great. The two primary objectives are low cost to produce and high hash rate. The original company is no longer producing these. I am also okay with a higher hash rate per board with more chips if you have already designed something similar. I just need to get to market quickly. I need design, component list, gerber file and anything else necessary to produce. Also, if you have a pcb manufacturer you prefer or would recommend then I am open to talking with them. Recreating this board (or similar) is the first st...

I need someone that can create and help maintain linux drivers for a video capture card that does not have linux drivers. I have the firmware for the card, I have the source code of the drivers for windows. I have the instructions in english and Russian for the FPGA card. The card will need to work in linux as a capture card for both types of input, ASI and SDI. Preferred that you know what that is, but I suspect that it is not 100% required. Please don't waste my time with useless bids. I expect you to show me proof that you have done something similar to this before. I will only select a winner once I know 100% you are able to handle the job. I will expect you to be able to do this remotely via ssh/terminal and remote KVM, I am available every day to work with...

...image processing synthesizable on xilinix nexys2 spartan 3e kit. I'd love a complete core for DCT/IDCT which an file could be instantiated and initilize on block ram of FPGA (or any other suitable methods of loading the image file on FPGA). The idea is to connect an INPUT_FRAME_BUFFER RAM which loads 8x8 blocks into DCT/IDCT core and an OUTPUT_FRAME_BUFFER RAM which stores 8x8 blocks output. Here's an idea of what I would like to implement on the FPGA hardware... I have a 240x160 pixel data stored in a .coe file or which will be instantiated and initialized in a block ram on the fpga . I want to load 8x8 blocks into the core and store 8x8 blocks of output, hence, the need for the input and ouput buffers. I want to perform t...

VHDL implementation of DCT/IDCT for image processing synthesizable on xilinix spartan 3e starter kit. I'd love a complete core for DCT/IDCT which an file could be instantiated and initilize on block ram of FPGA (or any other suitable methods). The idea is to connect an INPUT_FRAME_BUFFER RAM which loads 8x8 blocks into DCT core and an OUTPUT_FRAME_BUFFER RAM which stores 8x8 blocks output. More details will be provided.

Content:• Management Algorithms "write-through" and "write-back" it should work on fpga -SPARTAN 3e (in VHDL)

The aim of this project is to design ...digital circuit that enables to find the minterms of a given Karnaugh map. You should design the circuit by using Verilog and implement on the FPGA boards in the laboratory. You will be given the truth table and you will give the information on the truth table as inputs to the system. Your circuit will determine minterms of the system as sum of products or product of sums. There will be another control on your circuit that will determine the type of function. You will also implement the same problem by using NAND gates only and give the function. The circuit will give outputs and you will use seven segment displays on the Xilinx FPGA board to represent the outputs. Your outputs on the screen will be the letters that repr...

I need the software for a spartan3 fpga that takes a sample array and calcualtes the rms value. Code of the sample aquisition is given and all paremeters are available upon request.

adding more options to FPGA project using spartan 6 with documentation and adding more options to User interface using java

Need an electrical engineer who can design a PCB, and provide simulations along with best chips to use / costs. The final build will be to create a dual FPGA litecoin/bitcoin miner unit (so both SHA-256 and Scrypt) The FPGA unit would need help from on-board RAM, so you would need to have some understanding of utilising the RAM for processing as well. The software that will run on the FPGA is already created and open-source:- The base Experience in:- Litecoin / Bitcoin Designing PCBs using FPGAs, SoCs, high speed network interfaces and analogue/RF signal filtering. FPGA build with PCB design (Gerber) Chip communication protocol Prototyping with different chips (SIM via ISE is fine) Xilinx BOM VHDL / C / Python

Engineer with proven track record on the Altera Cyclone 2 - EP2C5F256C8N FPGA and preferably on the FTDI Morph-IC-ll board. Project requires the FTDI Morph-IC-ll board managing 4x24bit a/d converters scanning for data and the result delivered via USB to a host PC 100,000 times per second. Data can be chunked in blocks for expediency. A daughter board will be designed to piggyback the FTDI Morph-IC-ll board and to contain the a/d AD7764/7765 converters, you will be required to sketch this up and nominate the ports used for the sport interface. Do NOT apply if you do NOT have experience on this FPGA family. Your budget project quotation will be appreciated. Ole Hansen

adding more options to FPGA project using spartan 6 with documentation and adding more options to User interface using java

...engineer who can design a PCB, and provide simulations along with best chips to use / costs. The final build will be to create a FPGA litecoin miner unit (not bitcoin as this works different compared to Bitcoin sha256, litecoin uses scrypt) The FPGA unit would need help from on-board RAM, so you would need to have some understanding of utilising the RAM for processing as well. The software that will run on the FPGA is already created and open-source:- The base Experience in:- Litecoin / Bitcoin Designing PCBs using FPGAs, SoCs, high speed network interfaces and analogue/RF signal filtering. FPGA build with PCB design (Gerber) Chip communication protocol Prototyping with different chips (SIM via ISE is fine) Xilinx BOM

adding more options to FPGA project using spartan 6 with documentation and adding more options to User interface using java

hye.. im doing project on how to configure the ADC and DAC on DE2 Board and also write the verilog code for both ADC and DAC using Altera DE2 Board..

* FPGA core (Verilog is prefered) for AES 256 encryption/decryption is required from the freelancer. * Minimum 300 Mbps data rate is required * Simulation core and documentation is also required

This project is to make a small USB MODULE, which can operate on the GMRS / FRS / MURS frequencies and spectrum. This module should be powered by the USB port. It should have the property support for the channels and frequency's. It should be able to transmit some form of data on those frequency's and communication in various modes such as duplex and etc. The module it self has no buttons. It only has a MICRO USB connector for the PC. The PC software will allow talking, sending data through the module. It will allow changing the power output of the module, channels, frequency as needed. Sending data is to other module or device. Talking is to those standard walkie talkie devices on the market that use GMRS / FRS / MURS.

Hello! I am servhing someone who can build a bitcoin mining rig for me. Asic or fpga. Rig should have about 10 ghash.

I am working on the image processing cum fpga project. The title is Multiresolution Pyramid Construction on FPGA. Basically, its like storing an image(pixel values) in the fpga memory and displaying it on the vga monitor, this work is done and now i have to reduce the the size of the image and again store it back to the memory. Can I get any help regarding this?

You will need to create a GMRS / FRS / MURS / VHF/ UHF module with a simple pc based interface for data / voice communications. You can use either a combination of standard IC's or create a simple IP code for a cheap FPGA. Parts count must be as little as possible.